Data Movement

What Is Data Movement?

In modern systems-on-chip (SoCs) and chiplet-based architectures, data movement refers to the transport of information — such as transactions, cache lines, and memory reads/writes — between processing elements (CPUs, GPUs, NPUs), on-chip caches, shared memories, I/O peripherals, and external memory interfaces via the on-chip interconnect fabric.

As SoCs scale to include tens or hundreds of heterogeneous cores, multiple memory hierarchies, and multi-die configurations, the cost of moving data increasingly dominates the cost of compute. Industry analyses show that data movement can consume up to 80% of total SoC energy, far exceeding that spent on arithmetic operations. Every additional hop, router stage, or wire segment contributes to latency, power, and routing congestion — often determining system-level performance and energy efficiency more than the compute units themselves.

In short, data movement has become the fundamental bottleneck in advanced SoCs and chiplet systems, affecting energy, latency, and scalability.

Why It Matters

• Energy & Power Efficiency
  Every bit transferred over on-chip wires and routers consumes dynamic and leakage power. With advanced nodes and long interconnect lengths, wire energy becomes a dominant contributor to total dynamic power. Optimizing data movement — by reducing wire length, router count, and congestion — directly translates into system-level power savings.
  • Arteris customers, such as Samsung, report using FlexNoC to reduce power and die area in complex SoCs with over 100 IP blocks.
  • Studies (IJRTI, “AXI Interconnect-based NoC in SoC Devices,” 2025) demonstrate a latency and power improvement of ~25–30% over legacy bus architectures.
• Latency & Throughput
  High hop counts, congestion, and suboptimal routing degrade throughput. For AI, real-time vision, and memory-bound workloads, each nanosecond of delay compounds across billions of operations.
  • Mobileye notes that Arteris FlexNoC “enables high-bandwidth on-chip communication and load-balanced data traffic to off-chip memory, simplifying timing closure.”
  • Arteris’s physically aware NoC synthesis (FlexNoC 5) shortens critical paths and helps customers achieve timing closure faster, even in high-frequency SoCs.
• Routing Congestion & Wire Count
  Traditional point-to-point interconnects explode in wire count as IPs grow. A Network-on-Chip (NoC) fabric reduces total wire length by up to 50%. It lowers congestion hotspots, according to Arteris design-reuse data, leading to more predictable place-and-route convergence and lower area overhead.
• Scalability & Iteration Speed
  Manual interconnect design does not scale. Automated topology generation enables faster iteration and better physical convergence. Arteris’s FlexGen Smart NoC IP can reduce interconnect design cycles by up to 10 times, automating the optimization of wire length, timing, and power across hundreds of endpoints.

How Arteris Addresses Data Movement

Arteris’s suite of interconnect and integration IP — including FlexGen/FlexNoC, Ncore, and CodaCache — optimizes and orchestrates data movement across increasingly complex, multi-die SoCs.

• Protocol-agnostic Transport via NIUs
  Each IP connects through a Network Interface Unit (NIU), translating local protocols (AXI, AHB, CHI, OCP, or custom) into a packetized transport layer. This abstraction decouples the transport network from the protocol layer, enabling plug-and-play integration and easier reuse across designs and product generations.
• Physically Aware, Timing-Driven Topologies
  The FlexNoC 5 Physically Aware NoC integrates with physical design tools, taking into account floorplan constraints, wire lengths, and timing data. This reduces wire length, buffer count, and ECO loops, often shortening backend timing closure by weeks. Arteris reports up to 30% reduction in total wire length and improved layout convergence across large AI and automotive SoCs.
• AI-Assisted Topology Generation
  The FlexGen Smart NoC IP uses AI-driven search and heuristic optimization to explore candidate topologies, minimizing latency, congestion, and wire overhead. The result is up to 10× faster iteration and higher-quality solutions than manual exploration — a key enabler for AI and automotive designs that require rapid architectural prototyping.
• Modular, Tiled ScalabilityArteris supports tiled or modular NoC construction, ideal for scaling GPU/NPU compute arrays and multi-cluster CPU complexes. Regular topologies simplify verification, reduce integration risk, and support incremental scaling across die boundaries or new SKUs.
• QoS, Virtual Channels & Traffic Isolation
  FlexNoC embeds Quality of Service (QoS) controls, virtual channels, and congestion management to prevent interference among real-time, best-effort, and background traffic classes. This maintains predictable latency and bandwidth — critical for ADAS, AI, and automotive workloads with strict safety requirements.
• Integration with Caching & Coherency
  Arteris’s Ncore Coherent Interconnect and CodaCache IP coordinate tightly with the NoC to reduce unnecessary data movement. By reusing data locally, filtering snoops, and maintaining coherence hierarchies, they minimize off-chip memory access, dramatically cutting bandwidth and power consumption.

When Data Movement Optimization Is Critical

• AI / Machine Learning Workloads
  AI inference and training are primarily dominated by tensor memory movement, rather than arithmetic. Optimized NoC fabrics can double effective throughput by eliminating memory bottlenecks and improving reuse. Arteris solutions are deployed in Mobileye’s autonomous vision SoCs and leading AI accelerators for precisely this reason.
• Chiplet / Multi-Die Systems
  As systems partition across dies, die-to-die interconnect efficiency becomes crucial. Arteris supports multi-die topologies that integrate with UCIe and proprietary interposer links, thereby minimizing the latency and power penalties associated with crossing dies.
• Heterogeneous Systems / Many IP Blocks
  Modern SoCs contain hundreds of IP cores — including CPU clusters, GPUs, accelerators, and memory controllers. Arteris’s modular NoC simplifies connectivity and enables incremental scaling without global redesign.
• High Frequency / Tight Timing Budget Designs
  Physically aware synthesis and hierarchical floorplanning enable designers to achieve timing closure on paths exceeding 1 GHz while keeping congestion manageable — a vital requirement for advanced automotive, networking, and HPC designs.

Benefits & Metrics

In Summary

Arteris’s NoC technology transforms data movement from a bottleneck into a design advantage, replacing rigid bus structures with adaptive, power-efficient, and physically optimized fabrics. Industry data, customer testimonials (Mobileye, Samsung, Freescale), and peer studies all affirm that efficient data movement is now the decisive factor in SoC performance, power, and scalability.