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Semiconductor Engineering: The Future Of SoC Design Is Data Movement
The semiconductor industry is shifting from focusing on raw compute to tackling the growing challenge of data movement in complex SoCs. With advances in chiplets, high-bandwidth memory, CXL fabrics, and automotive zonal architectures, predictable performance now depends on layered, automated,
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Electronic Design: Speeding the Process of Building IPs, Chiplets, and SoCs
Designing modern SoCs and multi-die systems requires faster integration of thousands of IP blocks and chiplets while minimizing errors. Structured metadata standards like IP-XACT, combined with automation, are transforming this process by ensuring consistency, tool interoperability, and accurate hardware/software alignment
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Critical Safety Overview and Definitions
Critical Safety Overview and Definitions
Overview of critical safety systems and functional safety standards in automotive, focusing on ISO 26262 compliance and its impact on SoC design and performance.
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NoC Interconnect Fabric IP Improves SoC Power, Performance and Area
NoC Interconnect IP Improves SoC Power, Performance and Area
Explore how Arteris' NoC interconnect IP enhances SoC power efficiency, performance, and area, driving advancements in complex semiconductor designs.
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High-level representations of common NoC Topologies
SoC Interconnect Fabric: A Brief History from Buses to the NoCs of Today and Tomorrow
Explore the evolution of SoC interconnect fabrics from buses to advanced NoCs, highlighting their impact on modern high-performance computing and efficient system integration.
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Efficient IP Packaging for Today’s SoC Integration
Design & Reuse: Efficient IP Packaging for Today’s SoC Integration
As SoC architectures scale in complexity, managing hundreds of IP blocks consistently from concept through production is critical to avoid costly errors and rework. Standardizing IP descriptions with IEEE 1685 (IP-XACT) and automating packaging ensures interoperability, accelerates design, and promotes
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A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
Semiconductor Engineering: A Smarter Path To Chiplets Through An Enhanced Multi-Die Solution
With monolithic SoCs reaching their limits, chiplet-based architectures are key to building flexible, high-performance systems. Arteris’ multi-die solution combines silicon-proven NoC IP, cache coherency, and automation tools to streamline chiplet integration and accelerate time-to-market. Learn more in the article.
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Arteris’ Multi-Die Solution for the RISC-V Ecosystem
RISC-V: Arteris’ Multi-Die Solution for the RISC-V Ecosystem
As AI, HPC, and automotive workloads push past the limits of monolithic SoCs, chiplet-based design offers a scalable and cost-efficient path forward. Arteris enables this shift with advanced NoC IP for coherent and non-coherent multi-die interconnects, UCIe-based die-to-die links, and
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Magillem Packaging workflow
Semiconductor Engineering: System Integration With Standards-Based Automation
As SoCs evolve into complex multi-die systems, standards-based automation is key. Learn how IP-XACT and Arteris’ Magillem tools enable consistent metadata, scalable IP reuse, and faster, error-free integration across teams and tools.
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Why Chiplets Win for Al-based Semiconductors
EDN: Chiplet design basics for engineers
As AI and HPC workloads intensify, engineers are turning to chiplet-based architectures to overcome the limitations of traditional SoCs. This article explains the fundamentals of chiplet design, its advantages, and the tools enabling scalable, high-performance multi-die systems.
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