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Magillem Platform

Single source of truth environment for system design

Magillem Platform

Overview

Accelerating Time to Revenue with Magillem End-to-End Flow

Magillem Platform provides a unified design flow, empowering design teams with a radically improved process: easier, faster, and less risky.

It addresses the different steps of the design flow:

Magillem Packaging: Eases reuse and integration of various content from different sources, thanks to standards-based IP description automation with built-in ability to validate this incoming data, ensuring IP Integrity.
Magillem Connectivity: Streamlines and accelerates the SoC assembly with a robust and portable design process used by all teams, maximizing collaborative work and data accuracy.
Magillem Registers: Completing the integration flow, it addresses the Hardware/Software Interface automation to guarantee the address map is self-consistent and the auto-generated collaterals are of the highest quality, minimizing risks downstream.

Based on a single source of truth environment, this fully automated design flow ensures higher productivity and quality with a consistent end-to-end design flow solution.

Advantages

Comprehensive solution to simplify the design of complex SoCs

Based on an automated design flow wherein relevant teams can collaborate effectively to accelerate SoC development while mitigating design risks

Smooth and Efficient Process

Powerful automation reduces effort, rework and errors

Promote Design Reuse

With a true IP reuse methodology

Shorten Time to Market

Accelerate SoC connectivity and HSI development

Derisk SoC Design

Unified environment to ensure accuracy and cross-team consistency

Higher Quality

Earlier bug fixes thanks to robust error checking

Productivity Gains

Frees engineers from tedious tasks to focus on true innovation

Features

Magillem Platform Key Features

SoC Integration / Platform Assembly

IP and Design Reuse

HW / SW Interface – Register Management

Design Flow Automation – CAD Flow

Products

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SoC Connectivity

Magillem Connectivity

Shorten, streamline, and de-risk the integration process through automation and built-in checkers to boost productivity, accelerating TTM and improving design quality.

Hardware / Software Interface

Magillem Registers

Import memory map description in a single source of truth environment, ensuring synchronization between HW, SW, and documentation for automatic, consistent data generation.

Packaging

Magillem Packaging

A fully automated solution to import legacy RTL and create correct by-construction IP-XACT description, map the physical ports into bus interface, and capture the memory map.

Magillem Platform

Arteris SoC Integration Automation with the Magillem Platform

Learn about the powerful combination with Magillem Connectivity and Magillem Registers.

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog support
	SystemVerilog support
	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
	Checkers waivers and contextual help
Assembly	Rule-based connectivity
	Bus/signal split/tie/open
	Hierarchical connection
	Glue logic insertion
	Feedthrough
RTL Netlist Generation	Verilog and SystemVerilog support
	Configurable header
	Keep parameter expressions
	Deep netlist
	Signals/netname management
	Automatic tie of unconnected inputs
Hierarchical Manipulations	Merge, Flatten, Move operations
	Virtual hierarchy
	Component stubbing operation
	Hierarchical parameter propagation
	Design statistic reporting
IP Update	Interface/port/parameter renaming/resizing/deletion/merging
	User mapping rules definition
	Automatic tie connection generation on new ports
	Automated correct-by-construction IP-XACT platform update at any level of hierarchy
	Component instance view update
Diff and Merge	List concurrent conflicts/changes
	Accept/Reject any change
	Conflict resolution wizard (choice selection, instance renaming…)
	On-the-fly checks to verify the validity of choices/conflict resolution
Import Memory Map Description	CSRSpec support
	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description
	Excel spreadsheet

NoC Integration Automated Flow

Automated flow to leverage SoC connectivity information:

Improved productivity with reduced process
Better quality with early errors detections thanks to the checkers

NoC Integration Automated Flow

Customer Testimonials

Trusted by innovative
 companies everywhere

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.

Resources

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Infographic

Webinar

Datasheet

Video

Presentation

Podcast

White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.

Featured Solution

Arteris accelerates AI-driven silicon innovation with its expanded multi-die solution

Foundational technology for rapid chiplet-based design.

Flexible design scalability
Differentiated AI performance
Aligned with evolving industry standards

Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.